High accuracy timing parameter measurements are necessary to analyze and qualify devices and signals in a wide variety of electronic application. Such applications include clocks, PLLs, serial I/O jitter, skew, etc. A number of strategies have been used in practice for such measurements, including real-time oscilloscopes, equivalent-time oscilloscopes, offset frequency digital or analog under-sampling, and time interval analysis. Although each method has its own pros and cons for specific applications, TIA methods provide fairly general timing/jitter measurement methodologies that provide high accuracy with fast measurement times that cover a wide variety of applications.
TIAs are grouped into two general types: Start-to-Stop time interval analyzers and time stamp analyzers. Start-to-Stop time interval analyzers correspond to devices where only the timing of a START event is measured relative to a previous STOP event. Time stamp analyzers, often referred to as “time stampers,” correspond to instruments where all event timings are measured relative to a unique reference.
A more advanced form of time stamper is a continuous time interval analyzer (CTIA). CTIAs include a continuously running arming circuit to select events to be measured in a programmable fashion as well as potentially having more than one time stamper to measure the timing of multiple events that can be arbitrarily close in time in one measurement.
Most TIAs, whether continuous or not, include at least one high-resolution time interval measurement circuit. Such circuits include a reference clock counter to count the number of a precise clock cycles within the time interval of interest and an interpolator to measure any residual time less than one cycle of the reference clock. Multiple circuit techniques have been used to implement such circuits. These techniques generally include delay chain techniques, vernier delay line methodologies, vernier oscillator implementations, and time to voltage converter techniques.
Delay chain techniques quantize the time interval with a quantization step equivalent to a unit gate delay. The resolution of such method is usually limited to a few tens of picoseconds.
Vernier delay line methods use the delay difference between two delay elements to quantize time. They provide higher measurement resolution, but may suffer from excessive non-linearity and limited measurement range. This is more suitable for on-chip implementations due to large number of delay elements required.
Vernier oscillator methods rely on the difference between two oscillators' periods to quantize given time interval. Several implementations have been proposed in the literature. This method requires oscillators that can be switched on and off quickly without incurring significant noise and time-dependent non-linearity.
Time to voltage converters (TVC) are generally configured to charge or discharge a capacitance during the time interval of interest. The resulting voltage at the end of the time interval indicates the time interval or it's residual relative to a reference clock. A number of implementations have been proposed in the literature. Among the above methods, the TVC methods lend themselves more easily to off-chip implementation, however, a need remains for improvements in accuracy and resolution while providing short measurement time.
Continuous time interval analyzers (CTIA) such as Guidetech GT4000 use time stamping, arming, and event tracking for performing a wide variety of timing/jitter measurements accurately and quickly. One major part of the GT4000 is a time stamp generator (TSG), which measures the timing of an event of interest in a signal with very high resolution and precision. The combination of time stamp and event number forms a time tag for an event.
An exemplary time stamp generator (TSG) operation is shown in FIG. 1. Those of ordinary skill in the art would appreciate that in accordance with such operation an arming circuit 100 selects an edge to be stamped. The TSG uses an accurate and stable time base 110 and a counter 120 to measure the event timing with a resolution of one time base cycle. An interpolator circuit 130 then measures the event timing to the closest subsequent edge of the time base. The combination of interpolator 130 and time base counter 120 allow measurement of the timing of the selected edge. Digital Logic circuit 140 is configured to combine signal N from counter 120 with signal TP from Interpolator 130 to produce Time Stamp T. A typical timing measurement instrument may include more than one TSG to allow measuring parameters that require stamping two or more edges that may be very close to each other.
The interpolator resolution and inherent error specify the major parameters of the TSG. Today's high speed clocks and serializer/deserializer (SERDES) devices require better than 1 picosecond resolution and precision to perform meaningful measurements. Also, high effective sampling rate of the time tag generator is desired because it increases test throughput for some measurements, such as single period measurements. It can also substantially improve measurements such as phase noise, and jitter separation and filtering.
Time-to-voltage based interpolator circuit architecture is known which allows measuring the edge timing with high accuracy within a few picoseconds and fairly quickly within a few hundred nanoseconds. Such known circuitry is exemplified by U.S. Pat. No. 6,091,671 to Shalom Kattan, which is assigned to the owner of the present subject matter and incorporated herein by reference for all purposes. However, to address the growing need of today's high-speed signal test requirements, it has become desirable to improve the resolution, accuracy, and precision to better than 1 picosecond and measurement time of less than 100 nanoseconds.
While various implementations of time interpolators have been developed, no design has emerged that generally encompasses all of the desired characteristics as hereafter presented in accordance with the subject technology.